Process method to facilitate silicidation

ABSTRACT

The present invention substantially removes dry etch residue from a dry plasma etch process  110  prior to depositing a cobalt layer  124  on silicon substrate and/or polysilicon material. Subsequently, one or more annealing processes  128  are performed that cause the cobalt to react with the silicon thereby forming cobalt silicide regions. The lack of dry etch residue remaining between the deposited cobalt and the underlying silicon permits the cobalt silicide regions to be formed substantially uniform with a desired silicide sheet and contact resistance. The dry etch residue is substantially removed by performing a first cleaning operation  112  and then an extended cleaning operation  114  that includes a suitable cleaning solution. The first cleaning operation typically removes some, but not all of the dry etch residue. The extended cleaning operation  114  is performed at a higher temperature and/or for an extended duration and substantially removes dry etch residue remaining after the first cleaning operation  112.

FIELD OF THE INVENTION

The present invention relates generally to semiconductor devices, andmore particularly, to systems and methods to facilitate silicidationduring semiconductor device fabrication.

BACKGROUND OF THE INVENTION

Semiconductor devices such as, complementary metal oxide semiconductor(CMOS) devices, make extensive use of interconnects and contacts thatshould be scaleable to allow smooth migration to smaller geometries.Connections to and between active CMOS FET devices are typically createdwith “silicide” regions wherein a portion of a source/drain region isconverted during a thermal treatment into a metallic low resistanceregion.

Silicide regions are typically formed on active regions and on polygates. Generally, silicide regions are formed by depositing a refractorymetal, such as Titanium (Ti), on the active regions and gates. Heat isapplied and the refractory metal reacts with the underlying polysiliconand/or silicon layers by an alloy step forming silicide. Unreactedrefractory metal is then removed from the surface of the device. Theformed silicide regions provide low resistance regions that can becontacted by metal/conductive interconnects typically formed later.

A common mechanism to form silicide regions involves utilizing Titanium(Ti) as a refractory metal to react with Silicon (Si) to formTitanium-silicide (TiSi₂) on gate and active regions. However, TiSi₂ hasseveral limitations including, but not limited to, line-width dependentsheet resistance and bridging effect that causes high leakage current.

Another mechanism to form silicide regions employs Cobalt (Co) as arefractory metal to react with Silicon to form Cobalt-silicide (CoSi₂).An advantage of CoSi₂ over TiSi₂ is the extendibility of CoSi₂ tosmaller CMOS devices. However, formation of Cobalt-silicide can beproblematic. For example, cobalt is sensitive to oxygen and water. As aresult, formed Cobalt salicide (self aligned silicide) can becontaminated with oxygen and/or water, thereby increasing sheetresistance of the formed Cobalt salicide even if relatively pure inertgas is employed for the heat treatment. One technique employed to reducethis oxidation of cobalt salicide is to form a Titanium (Ti) and/or aTitanium-nitride (TiN) cap layer on top of deposited cobalt prior to itsreaction with underlying silicon and/or polysilicon.

Typically, a cobalt layer is deposited on/over a wafer having a topsurface comprised of a mixture of exposed surfaces including dielectricsurfaces and silicon surfaces. A Ti or TiN cap layer is deposited on theCo layer without exposing the cobalt layer to air. Subsequently, thewafer is subjected to a first annealing process during which the cobaltreacts with silicon at the surface of the wafer where silicon orpolysilicon is in contact with the cobalt layer. After the first anneal,the wafer is etched in a NH₄OH, H₂O₂, H₂O solution and then with aH₂SO₄, H₂O₂, H₂O solution. This two-step wet etch process attempts toremove un-reacted cobalt and Ti or TiN. Then, a second anneal isperformed to complete the cobalt salicide formation process.

The use of a Ti cap layer has been shown to mitigate oxygencontamination. However, other problems can result from the inclusion ofthe Ti cap layer in the salicide formation process. For example, Ti candiffuse into the cobalt layer during the first anneal, resulting inmediation of the silicidation reaction by Ti. Thus, the presence of Tiretards the cobalt-silicon reaction so that higher anneal temperaturesmay be required to complete the reaction. Additionally, some of the Tican react with cobalt forming an unwanted CoTi inter-metallic mixturelayer that causes high sheet resistance. Additionally, the presence ofTi and/or TiN can reduce the amount of cobalt available to react withunderlying silicon.

SUMMARY OF THE INVENTION

The following presents a simplified summary in order to provide a basicunderstanding of one or more aspects of the invention. This summary isnot an extensive overview of the invention, and is neither intended toidentify key or critical elements of the invention, nor to delineate thescope thereof. Rather, the primary purpose of the summary is to presentsome concepts of the invention in a simplified form as a prelude to themore detailed description that is presented later.

The present invention facilitates cobalt silicide region formation insemiconductor devices. As a result, desired resistances for formedcobalt silicide regions can be obtained, even for relatively small sizedsemiconductor devices.

The present invention substantially removes dry etch residue from a dryplasma etch process prior to depositing a cobalt layer on a siliconsubstrate and/or polysilicon material. Subsequently, one or moreannealing processes are performed that cause the cobalt to react withthe clean silicon surface, thereby forming cobalt silicide regions. Thelack of dry etch residue remaining between the deposited cobalt and theunderlying silicon permits the cobalt silicide regions to be formedsubstantially uniform with a desired resistance.

The dry etch residue is substantially removed by performing a firstcleaning operation and then an extended cleaning operation that includesa suitable cleaning solution. The first cleaning operation typicallyremoves some, but not all of the dry etch residue. The extended cleaningoperation is performed at a higher temperature and/or for an extendedduration and substantially removes dry etch residue remaining after thefirst cleaning operation.

This extended clean is performed immediately after the dry plasma etchand prior to the heavy source/drain implants. To the accomplishment ofthe foregoing and related ends, the invention comprises the featureshereinafter fully described and particularly pointed out in the claims.The following description and the annexed drawings set forth in detailcertain illustrative aspects and implementations of the invention. Theseare indicative, however, of but a few of the various ways in which theprinciples of the invention may be employed. Other objects, advantagesand novel features of the invention will become apparent from thefollowing detailed description of the invention when considered inconjunction with the drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A and 1B are a flow diagram illustrating a method of fabricatinga semiconductor device in accordance with an aspect of the presentinvention.

FIG. 2A is a cross sectional view of an exemplary semiconductor deviceafter etching with a dry etch plasma etch process in accordance with anaspect of the present invention.

FIG. 2B is a cross sectional view of an exemplary semiconductor deviceafter performing a first cleaning operation in accordance with an aspectof the present invention.

FIG. 2C is a cross section view of an exemplary semiconductor deviceafter performing an extended cleaning operation in accordance with anaspect of the present invention.

FIG. 2D is a cross sectional view of an exemplary semiconductor deviceafter formation of active regions in accordance with an aspect of thepresent invention.

FIG. 2E is a cross sectional view of an exemplary semiconductor deviceafter depositing a layer of cobalt on the device in accordance with anaspect of the present invention.

FIG. 2F is a cross sectional view of an exemplary semiconductor deviceafter forming a cap layer in accordance with an aspect of the presentinvention.

FIG. 2G is a cross sectional view of an exemplary semiconductor deviceafter formation of silicide regions in accordance with an aspect of thepresent invention.

FIG. 2H is a cross sectional view of an exemplary semiconductor deviceafter removal of the un-reacted cobalt layer and TiN layer in accordancewith an aspect of the present invention.

FIG. 3 is a flow diagram illustrating a method of fabricating asemiconductor device with substantially uniform cobalt silicide regionsin accordance with an aspect of the present invention.

FIG. 4 is a flow diagram illustrating a method of fabricating asemiconductor device with substantially uniform cobalt silicide regionsin accordance with an aspect of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

The present invention will now be described with respect to theaccompanying drawings in which like numbered elements represent likeparts. The figures provided herewith and the accompanying description ofthe figures are merely provided for illustrative purposes. One ofordinary skill in the art should realize, based on the instantdescription, other implementations and methods for fabricating thedevices and structures illustrated in the figures and in the followingdescription.

The present invention substantially removes dry etch residue resultingfrom a dry plasma etch process prior to depositing a cobalt layer on asilicon substrate and/or polysilicon material. Subsequently, one or moreannealing processes are performed that cause the cobalt to react withthe silicon thereby forming cobalt silicide regions. The lack of dryetch residue remaining between the deposited cobalt and the underlyingsilicon permits the cobalt silicide regions to be formed substantiallyuniformly and with a desired contact resistance, particularly forreduced contact pitch semiconductor devices.

FIG. 1 is a flow diagram illustrating a method 100 of fabricating asemiconductor device in accordance with an aspect of the presentinvention. The method 100 mitigates contamination of cobalt duringsilicidation by employing an additional cleaning operation that removesresidue. By mitigating contamination, a more uniform cobalt silicidecontact/region can be formed, particularly for devices with relativelysmall contact to poly spacing of 200 nm or less pitches.

FIGS. 2A through 2H are provided and described below to illustrate anexemplary semiconductor device 200 fabricated by way of the method 100of FIG. 1. The FIGS. 2A through 2H serve to further illustrate themethod 100 by depicting exemplary layers as they are formed during themethod 100. However, it is appreciated that substantial variations instructure and composition can occur in semiconductor device formed fromthe method 100 and variations thereof and yet be in accordance with thepresent invention.

The method 100 begins at block 102 wherein a silicon or semiconductorsubstrate or body is processed to form isolation regions (e.g., shallowtrench isolation regions (STI)). Then, wells are defined and can bedoped by selectively implanting desired dopants to form n-type and/orp-type well regions.

Gate stacks are formed at block 104 by depositing a gate oxide orinsulating layer on the semiconductor substrate, forming a polysiliconor conductive layer on the gate oxide layer, and patterning the gateoxide layer and the polysilicon layer to form the gate stacks. Thepolysilicon layer can also be lightly doped (n-type or p-type) in orderto facilitate operation of the device.

Offset spacers are formed adjacent the sidewalls of the gate structuresat block 106. The offset spacers are typically formed by depositing orgrowing a dielectric layer (e.g., oxide) and etching the depositeddielectric layer to leave the formed offset spacers. Extension regionsare then formed at block 108 by performing shallow implants atrelatively low energies with selected dopants to form the extensionregions.

Continuing with the method 100, sidewall spacers are formed at block 110by depositing a sidewall dielectric layer and etching the dielectriclayer via a dry etch plasma process to form the sidewall spacersadjacent to the gate stacks and the offset spacers. It is appreciatedthat formation of the sidewall spacers can include depositing multipledielectric layers of varied dielectric materials prior to patterning themultiple dielectric layers. Dry etch plasma processes are chemicalprocesses that use gas and plasma energy to cause the desired chemicalreactions. The dry etch plasma processes employ a chemical etchant andan energy source.

Dry etch plasma processes are performed within a chamber and typicallyinclude a vacuum system, gas supply, and a power supply. Thesemiconductor device (along with other semiconductor device or wafers)are loaded into the chamber and the pressure inside is reduced by thevacuum system. After the vacuum is established, the chamber is filledwith a reactive gas selected for the target material (e.g., CF₄ mixedwith oxygen for silicon dioxide). A power supply creates a radiofrequency (RF) field through electrodes in the chamber, which energizesthe reactive gas to a plasma state. In the energized, plasma state, ions(e.g., fluorine) attack the target material (e.g., silicon dioxide)converting the target material into volatile components that are removedby the vacuum system. An undesired result of the dry etch plasma processemployed to form the sidewall spacers is that dry etch residue from thereactant gas, target material, and volatile components can remain onsurfaces of the semiconductor device.

The inventors of the present invention have identified that this dryetch residue can negatively impact and/or prevent cobalt silicideformation and, therefore, result in an undesired increase in resistancein silicon and poly gate.

FIG. 2A is a cross sectional view of an exemplary semiconductor device200 after etching with a dry etch plasma etch process in accordance withan aspect of the present invention. The exemplary device 200 isfabricated via block 102 to 110 of the method 100 of FIG. 1. Isolationregions 204 are formed in a semiconductor substrate or body 202 anddefine, for example, a well region 206 that can be doped n-type orp-type. A gate oxide layer or other insulating layer 208 is formed onthe well region 206 and a polysilicon layer or other gate electrode 210is formed on the gate oxide layer 208. The gate oxide layer 208 and thepolysilicon layer 210 have been dry etched to define a gate stack 212.Offset spacers 214 are formed on sidewalls of the gate stack 212 and areemployed to form extension regions 207. Sidewall spacers 216 are formedadjacent the offset spacers 214 by depositing a dielectric layer andpatterning the dielectric layer with a dry etch plasma process. Dry etchresidue 218 can be present on surfaces of the extension regions 207and/or the polysilicon layer 210.

Referring again to FIG. 1A, a first cleaning operation is performed atblock 112 by cleaning a surface of the semiconductor device with amixture, for example, of ammonium hydroxide and peroxide(NH₄OH—H₂O₂—H₂O) having a ratio, for example, of 1:1:5. The firstcleaning operation is typically performed at a temperature of about 25to 60 degrees Celsius for a duration of about 3.5 minutes to 10 minutesvia a bath or a spray processor. However, it is appreciated that othertemperatures and durations can be employed such as, for example, atemperature of 60 degrees Celsius and a duration of 5 minutes in a bath,a temperature of 25 degrees Celsius and a duration of 10 minutes in abath, a temperature of 60 degrees Celsius and a duration of 3.5 minutesin a spray processor, and the like. The first cleaning operation removessome, but typically not all, of the remaining dry etch residue.

The inventors of the present invention have identified that theremaining dry etch residue after the first cleaning operation can bepresent and can degrade or prevent proper cobalt silicide formation. Theremaining dry etch residue, if not removed, can prevent cobalt andunderlying silicon from reacting. As a result, cobalt silicide regionscan be improperly formed leading to an undesirable increase in silicidesheet and also contact resistance.

FIG. 2B is a cross sectional view of an exemplary semiconductor device200 after performing a first cleaning operation in accordance with anaspect of the present invention. Even after the first cleaningoperation, some of the dry etch residue 220 can remain on surfaceportions of the extension regions 207 and/or the polysilicon layer 210.

An extended cleaning operation is performed at block 114 in order tosubstantially remove the remaining dry etch residue. As described above,the first cleaning operation 112 typically fails to remove all of theresidue from the dry etch employed to form the sidewall spacers. Theextended cleaning operation substantially removes any remaining dry etchresidue.

The semiconductor device and the wafer the device is formed upon areimmersed in the cleaning solution, typically along with other wafers asa batch immersion process. However, other suitable operations includesingle wafer processing and/or spraying the cleaning solution ontosurfaces of the device and wafer. Subsequently, a suitable dryingoperation is performed to dry the device and wafer, such as, for examplea spin dry.

One exemplary suitable extending cleaning operation employs a cleaningsolution comprised of ammonium hydroxide and peroxide (NH₄OH—H₂O₂—H₂O)and performs the cleaning operation for an extended period of timeand/or at a relatively high temperature. The ammonium hydroxide andperoxide cleaning operation is performed for a duration greater than orequal to about 5-20 minutes and is performed at a temperature of 50-70degrees Celsius. Additionally, the ammonium hydroxide and peroxide isgenerally more diluted than that employed in the first cleaningoperation. As an example, a suitable mixture of ammonium hydroxide andperoxide employed for the cleaning solution has a ratio forNH₄OH:H₂O₂:H₂O of about 1:1:20. The inventors of the present inventionappreciate that the extended period of time and/or temperature canrequire a more diluted solution of ammonium hydroxide and peroxide.

Another suitable extended cleaning operation employs a cleaning solutioncomprised of H₃PO₄. With this solution, an even higher temperature isemployed (e.g., about 120 degrees Celsius) for the extended duration(e.g., greater than about 10 minutes).

FIG. 2C is a cross section view of an exemplary semiconductor device 200after performing an extended cleaning operation in accordance with anaspect of the present invention. The extended cleaning operationsubstantially removes any remaining dry etch residue.

Active regions (source and drain regions) are formed at block 116 byselectively implanting n-type and/or p-type dopants. The implantation istypically performed with a higher energy than employed in forming theextension regions such that the active regions are deeper than theextension regions but not as deep as the formed well regions.Subsequently, an annealing operation is performed at block 118 tofacilitate formation of the active regions. In alternate aspects of theinvention, the first cleaning operation of block 112 and/or the extendedcleaning operation of block 114 can be performed after implanting then-type and/or p-type dopants at block 116, but before the annealingperformed at block 118.

FIG. 2D is a cross sectional view of an exemplary semiconductor device200 after formation of active regions 209 in accordance with an aspectof the present invention. The active regions 209 were formed andannealed as described in blocks 114 and 116 and extend below theextension regions 207.

Continuing with the method 100, a wet pre-clean operation is performedto remove native oxide from at least some surface portions of the activeregions at block 120. An example of a suitable process for the wetpre-clean operation includes processing the semiconductor device in anHF dip using deoxygenated water. Then, isopropyl alcohol is employed todry the device. The HF dip and the isopropyl drying can be performedrepeatedly. Another example of a suitable process for the wet pre-cleanoperation includes using an HF vapor treatment to remove the nativeoxide.

Subsequent the wet pre-clean operation of block 120, a reduced argonpre-clean operation, also referred to as a pre-sputter etch (PSE), isperformed at block 122 to remove remaining native oxide (not shown) leftafter the wet pre-clean operation performed at block 120. The reducedpre-clean operation is performed with a reduced amount of argon tomitigate removal of material from the sidewalls, which can result insidewall residue depositing from the sidewalls and onto the surfaceportions of the active regions and the gate stack. In one example, thereduced pre-clean operation is performed with 20+/−10 A PETEOSequivalent oxide removal. Conventional argon based sputter etches remove30 to 75 Angstroms of oxide. The reduced pre-clean operation removesless the 30 Angstroms (e.g., about 10 to 20 Angstroms). It isappreciated that other types of sputter etch can be performed inalternate aspects of the present invention. Furthermore, it is alsoappreciated that alternate aspects of the present invention can performthe method 100 without the sputter pre-clean operation of block 120.Additionally, the pre-cleaning operations of block 120 and 122 thatremove the native oxide can in other aspects of the invention beperformed prior to forming the active regions at block 116.

At block 124, cobalt is deposited over the device forming a layer ofcobalt material. A number of suitable cobalt deposition techniques canbe employed to form the cobalt layer. One such technique begins withplacing the semiconductor device in a sputter deposition chamber whereinthe cobalt material (e.g., about 10 nm) is deposited over the entiredevice using a substantially pure cobalt target in a noble gas plasmaenvironment.

FIG. 2E is a cross sectional view of an exemplary semiconductor device200 after depositing a layer of cobalt 226 on the device in accordancewith an aspect of the present invention. The cobalt layer 226 isdeposited in accordance with block 124 of the method 100 of FIG. 1. FIG.2E indicates that the dry etch residue 224 of FIG. 2F has beensubstantially removed by the pre-cleaning operations of blocks 118 and120. Additionally, the reduced sputter pre-clean operation of block 120has not removed portions of the sidewalls 216 and/or deposited removedportions of the sidewalls 216 onto surface portions of the extensionregions 207 and/or the polysilicon layer 210.

A cap layer is formed on the cobalt layer at block 126. The cap layercomprises a cap material such as Ti or TiN and serves to mitigate oxygencontamination of the cobalt layer. The cap layer is formed by depositingthe cap material via a suitable deposition process. An example of such aprocess involves placing the device in a chamber wherein the capmaterial is deposited via, for example, PVD to form a TiN cap layer witha thickness of about 15 nm in a nitrogen gas environment.

FIG. 2F is a cross sectional view of an exemplary semiconductor device200 after forming a cap layer 228 in accordance with an aspect of thepresent invention. The cap layer 228 is formed on the cobalt layer 226and comprises a suitable material that may mitigate oxygen contaminationof the cobalt layer 226. It is appreciated that other semiconductordevices fabricated in accordance with the present invention can foregoforming and using a cap layer.

A first anneal process is performed at block 128 in order to initiatesilicidation of cobalt and silicon thereby forming silicide regions.Typically, a rapid thermal process is typically performed for a durationof 10-100 Sec and at a temperature of 500-650 C.

FIG. 2G is a cross sectional view of an exemplary semiconductor device200 after formation of silicide regions 230 in accordance with an aspectof the present invention. The silicide regions 230 are formed ascobalt-silicide by a reaction between the deposited cobalt layer 226 andsurface portions of the extension regions 207 (or active regions 209)and the polysilicon layer 210. Silicon and cobalt react undertemperature to form the cobalt mono-silicide regions 230. The silicideregions 230 are formed as desired with substantial uniformity becausecontaminants such as the dry etch residue had been removed prior todepositing the cobalt layer 226.

Subsequent to formation of the silicide regions, remaining un-reactedportions of the cobalt layer are removed and the cap layer is removed atblock 130. A suitable etch process, such as a two step wet etch process,is employed to remove the unreacted portions of the cobalt layer and thecap layer. The two step etch comprises etching the semiconductor devicein a NH₄OH, H₂O₂, H₂O solution followed by an etch in a H₂SO₄, H₂O₂, H₂Osolution. Subsequently, a second anneal process is performed at block132 to complete formation of the silicide regions, which results in theformation of low resistance cobalt di-silicide. The second annealprocess is also typically a rapid thermal anneal process performed at atemperature of 650-900 C for a duration of 10-60 Sec.

After formation of the silicide regions additional processing steps aretypically performed to form additional layers and structures such as,for example, interlevel dielectric layers, metallization, and the like.

FIG. 2H is a cross sectional view of an exemplary semiconductor device200 after removal of the un-reacted cobalt layer 226 in accordance withan aspect of the present invention. The cobalt layer 226 and the caplayer 228 are removed as described at block 128 of the method 100 ofFIG. 1. Additional layers such as interlevel dielectric layers,metallization, and the like can be formed to complete fabrication of thedevice 200.

It is appreciated that variations in the blocks performed and the orderin which they are performed can vary. For example, the inventors of thepresent invention appreciate that the first cleaning operation can beomitted and only the extended cleaning operation be performed invariations of the method 100. Additionally, as another example, theinventors of the present invention appreciate that the extended cleaningoperation can be performed multiple times with varied cleaning solutionsin order to substantially remove the dry etch residue. However, it iscritical that the extended cleaning is done before the heavysource/drain ion implants.

FIG. 3 is a flow diagram illustrating a method 300 of fabricating asemiconductor device with substantially uniform cobalt silicide regionsin accordance with another aspect of the present invention. The method300 substantially removes dry etch residue prior to depositing a cobaltlayer by employing an extended cleaning operation with a mixture ofammonium hydroxide. As a result, formation of uniform cobalt silicideregions/contacts and reduced contact resistance can be obtained.

The method 300 begins at block 302 wherein a semiconductor device havinggate stacks formed on and active regions defined in a semiconductorsubstrate is provided. The defined active regions have not yet beenimplanted with a selected dopant to operate as source drain regions.Additionally, the active regions may also be referred to as diffusionregions.

An insulative layer (e.g., silicon dioxide) is formed over the activeregions and the gate stacks at block 304. Generally, the insulativelayer is formed by depositing a dielectric material over the device. Theinsulative layer is dry plasma etched at block 306 to remove portions ofthe insulative layer and form sidewall spacers adjacent sidewalls of thegate stacks. It is appreciated that formation of the sidewall spacerscan include depositing multiple layers of varied prior to dry etchingthe multiple layers. The dry plasma etch employs a chemical etchant thatis selective to the materials comprising the insulative layer and anenergy source to energize the chemical reactant to a plasma statewherein ions attack and etch exposed portions of the insulative layer byetching anisotropically. An undesired result of the dry etch plasmaprocess employed to form the sidewall spacers is that dry etch residuefrom the reactant gas, target material, and volatile components canremain on surfaces of the semiconductor device.

The semiconductor device is subjected to a first mixture of ammoniumhydroxide and peroxide at a relatively low temperature for a relativelyshort duration at block 308 to remove a portion of dry etch residue fromsurfaces of the semiconductor device. The relatively short durationcorresponds to about 3.5 minutes to about 10 minutes and the relativelylow temperature corresponds to about 25 to about 60 degrees Celsius. Themixture can be applied via an immersion bath and/or spray mechanism. Theoperation removes some, but not all, of the remaining dry etch residue.Subsequently, a suitable drying operation is performed to dry the deviceand wafer, such as, for example a spin dry.

Then, the semiconductor device is subjected to a second mixture ofammonium hydroxide and peroxide at a relatively high temperature for arelatively long duration at block 310 to remove remaining portions ofthe dry etch residue from surfaces of the semiconductor device. Therelatively long duration corresponds to at least about 10 minutes andthe relatively high temperature corresponds to at least about 60 degreesCelsius. The second mixture can be applied via an immersion bath and/orspray mechanism. The operation removes substantially all of theremaining dry etch residue. Subsequently, a suitable drying operation isperformed to dry the device and wafer, such as, for example a spin dry.

Active regions are selective implanted with dopants at block 312. Otherprocesses including native oxide removal via sputtering can also beperformed before or after the active region implantation.

A layer of cobalt is deposited at block 314, typically by sputteringcobalt on the device. A cap layer, typically in thickness range of 10-30nm, can optionally be formed on the cobalt layer in order to mitigateoxygen contamination of the cobalt. Cobalt silicide regions are thenformed by performing one or more anneals that cause the cobalt to reactwith underlying silicon and form cobalt mon-silicide (CoSi) at block316. The formed cobalt silicide regions are substantially uniform andprovide suitable contact resistance for operation of the semiconductordevice.

FIG. 4 is a flow diagram illustrating a method 400 of fabricating asemiconductor device with substantially uniform cobalt silicide regionsin accordance with an aspect of the present invention. The methodemploys a cleaning solution comprised of H₃PO₄ instead of the ammoniumhydroxide employed in the method 300 of FIG. 3. The method 400substantially removes dry etch residue prior to depositing a cobaltlayer, thereby facilitating formation of uniform cobalt silicideregions/contacts.

The method 400 begins at block 402 wherein a semiconductor device havinggate stacks formed on and active regions defined in a semiconductorsubstrate is provided. The defined active regions have not yet beenimplanted with a selected dopant to operate as source drain regions.Additionally, the active regions may also be referred to as diffusionregions.

Continuing with the method 400, an insulative layer (e.g., silicondioxide) is formed over the active regions and the gate stacks at block404. The insulative layer is formed by depositing a suitable insulativematerial over the device. The insulative layer is dry plasma etched atblock 406 to remove exposed portions of the insulative layer and formsidewall spacers adjacent sidewalls of the gate stacks. It isappreciated that formation of the sidewall spacers can includedepositing multiple layers of varied prior to dry etching the multiplelayers. The dry plasma etch employs a chemical etchant that is selectiveto the materials comprising the insulative layer and an energy source toenergize the chemical reactant to a plasma state wherein ions attack andetch exposed portions of the insulative layer. An undesired result ofthe dry etch plasma process employed to form the sidewall spacers isthat dry etch residue from the reactant gas, target material, andvolatile components can remain on surfaces of the semiconductor device.

The semiconductor device is subjected to a mixture of ammonium hydroxideand peroxide at a relatively low temperature for a relatively shortduration at block 408 to remove a portion of dry etch residue fromsurfaces of the semiconductor device. The relatively short durationcorresponds to about 4.5 minutes to about 10 minutes and the relativelylow temperature corresponds to about 25 to about 60 degrees Celsius. Themixture can be applied via an immersion bath and/or spray mechanism. Theoperation removes some, but not all, of the remaining dry etch residue.Subsequently, a suitable drying operation is performed to dry the deviceand wafer, such as, for example a spin dry.

Then, the semiconductor device is subjected to a cleaning solutioncomprised of H₃PO₄ at a relatively high temperature for a relativelylong duration at block 410 to remove remaining portions of the dry etchresidue from surfaces of the semiconductor device. The relatively longduration corresponds to at least about 10 minutes and the relativelyhigh temperature corresponds to at least about 120 degrees Celsius. Thecleaning solution can be applied via an immersion bath and/or spraymechanism. The operation removes substantially all of the remaining dryetch residue. Subsequently, a suitable drying operation is performed todry the device and wafer, such as, for example a spin dry.

Active region are selective implanted with dopants at block 412. Otherprocesses including native oxide removal via sputtering can also beperformed before or after the active region implantation.

A layer of cobalt is deposited at block 414, typically by sputteringCobalt on the device. A cap layer, typically in thickness range of 10-30nm, can optionally be formed on the cobalt layer in order to mitigateoxygen contamination. Cobalt silicide regions are then formed byperforming one or more anneals that cause the cobalt to react withunderlying silicon and form cobalt silicide (CoSi, CoSi₂) at block 416.The formed cobalt silicide regions are substantially uniform and providesuitable contact resistance for operation of the semiconductor device.

While, for purposes of simplicity of explanation, the methodologies ofFIGS. 1, 3 and 4 are depicted and described as executing serially, it isto be understood and appreciated that the present invention is notlimited by the illustrated order, as some aspects could, in accordancewith the present invention, occur in different orders and/orconcurrently with other aspects from that depicted and described herein.Moreover, not all illustrated features may be required to implement amethodology in accordance with an aspect the present invention.

Although the invention has been shown and described with respect to acertain aspect or various aspects, it is obvious that equivalentalterations and modifications will occur to others skilled in the artupon the reading and understanding of this specification and the annexeddrawings. In particular regard to the various functions performed by theabove described components (assemblies, devices, circuits, etc.), theterms (including a reference to a “means”) used to describe suchcomponents are intended to correspond, unless otherwise indicated, toany component which performs the specified function of the describedcomponent (i.e., that is functionally equivalent), even though notstructurally equivalent to the disclosed structure which performs thefunction in the herein illustrated exemplary embodiments of theinvention. In addition, while a particular feature of the invention mayhave been disclosed with respect to only one of several aspects of theinvention, such feature may be combined with one or more other featuresof the other aspects as may be desired and advantageous for any given orparticular application. Furthermore, to the extent that the term“includes” is used in either the detailed description or the claims,such term is intended to be inclusive in a manner similar to the term“comprising.”

1. A method of fabricating a semiconductor device comprising: forming a gate oxide layer on a semiconductor substrate; forming a polysilicon layer on the gate oxide layer; patterning the gate oxide layer and the polysilicon layer to form gate structures; forming offset spacers adjacent to gate stacks; performing an shallow region implant to form extension regions; depositing a dielectric layer and patterning the dielectric layer to form sidewall spacers adjacent to the gate stacks and the offset spacers via a dry etch plasma process that leaves dry etch residue; performing a first cleaning operation that removes a portion of the dry etch residue; performing an extended cleaning operation to substantially remove the dry etch residue after the first cleaning operation; performing an active region deep implant to form active regions after performing the first cleaning operation and the extended cleaning operation; performing an anneal operation to form the active regions; performing a wet pre-clean operation to remove a portion of native oxide from a surface portion of the active regions; performing a reduced sputter operation to substantially remove the native oxide that mitigates dislodging of sidewall materials from the sidewall spacers onto surfaces of the active regions; forming a cobalt layer on the device by depositing cobaly; forming a cap layer on the cobalt layer; performing a first silicide anneal to initiate formation of cobalt mono-silicide regions, wherein the cobalt-silicide regions are substantially uniform; removing the cap layer and the un-reacted cobalt; and performing a second silicide anneal to complete formation of the cobalt di-silicide regions.
 2. The method of claim 1, wherein the extended cleaning operation is performed at a greater temperature than the first cleaning operation.
 3. The method of claim 1, wherein the extended cleaning operation is performed for a longer duration than the first cleaning operation.
 4. The method of claim 1, wherein the extended cleaning operation is performed at a greater temperature than the first cleaning operation and is performed for a longer duration than the first cleaning operation.
 5. The method of claim 1, wherein performing the extended cleaning operation comprises subjecting the semiconductor device to a cleaning solution for a duration of at least 10 minutes and a temperature of at least 60 degrees Celsius.
 6. The method of claim 5, wherein the cleaning solution comprises a mixture of ammonium hydroxide and peroxide.
 7. The method of claim 5, wherein the cleaning solution comprises H₃PO₄.
 8. The method of claim 1, wherein the reduced sputter operation is performed by sputtering Argon for a reduced time period to remove a relatively small amount of oxide material thereby substantially removing the native oxide.
 9. The method of claim 8, wherein the small amount of oxide material removed is less than 30 Angstroms.
 10. The method of fabricating a semiconductor device comprising: depositing a dielectric layer and patterning the dielectric layer to form sidewall spacers adjacent to a gate stack via a dry etch plasma process that leaves dry etch residue; performing a first cleaning operation that removes a portion of the dry etch residue; performing an extended cleaning operation to substantially remove the dry etch residue after the first cleaning operation; performing an active region deep implant to form active regions after performing the first cleaning operation and the extended cleaning operation.
 11. The method of claim 10, wherein the extended cleaning operation is performed at a greater temperature than the first cleaning operation.
 12. A method of claim 10, wherein performing the extended cleaning operation comprises subjecting the semiconductor device to a cleaning solution for a duration of at least 10 minutes and a temperature of at least 60 degrees Celsius.
 13. The method of claim 12, wherein the cleaning solution comprises a mixture of ammonium hydroxide and peroxide.
 14. The method of claim 12, wherein the cleaning solution comprises H₃PO₄. 